发明名称 INPUT AND OUTPUT ADAPTOR
摘要 PURPOSE:To improve greatly a program executing performance by providing a timing monitor circuit for the discrimination of a foul DMA request and therefore cancelling the foul DMA request together with no malfunction of a DMA. CONSTITUTION:When the transfer of data is controlled between an I/O device and a main memory via an I/O adaptor, a DMA service request is sent first to a timing monitor circuit 6 from a data transfer control circuit 5. The circuit 6 discriminates whether said service request is right or foul. Then the circuit 6 prevents the transmission of the DMA service request to a DMA control circuit 7 as long as this request is foul. Instead a read/write control circuit 8 is driven. Thus the artificial reading or writing operation is carried out. Then the DMA service request given from the circuit 5 is cancelled.
申请公布号 JPS61112267(A) 申请公布日期 1986.05.30
申请号 JP19840233794 申请日期 1984.11.06
申请人 NEC CORP 发明人 NAKAMURA KOICHI
分类号 G06F13/00;G06F13/28 主分类号 G06F13/00
代理机构 代理人
主权项
地址