| 摘要 |
<p>PURPOSE:To simplify the constitution of a logical arithmetic unit together with an easy logic change by defining an address bus and a data bus as an input part and an output part respectively and furthermore using the signal of the input part to read out data after designation of an address. CONSTITUTION:An address bus 2 of a memory 3 is used as an input part for input of the (contact) signal input 8 of a logic selection part 1, the signal storage input 6, the timer signal 7, etc. The memory 3 produces a logic pattern according to those input conditions and delivers it to a data bus 4 serving as an output part. Some of the signals delivered via the bus 4 are supplied again to the memory 3 through the bus 2 directly as the input 6 or via timers 51 and 52 as the timer signal input 7. The part 1 selects a desired logic and therefore the memory 3 produces a logic in accordance with the input 8. Then a desired output 9 is obtained on the bus 4.</p> |
