| 摘要 |
PURPOSE:To reduce the size of a chip and to increase the integration of the chip by activating the gate electrode wiring layer of a block to enhance the utility of the intermediate wiring layer of the block of a chip center. CONSTITUTION:Since the wirings of a block 5 of the periphery of a chip are relatively small in the second layer wirings 10, 11 in a Y direction A1 between the blocks at the periphery of the chip, the second layer 9 in the block A1 is used. Accordingly, a cell 7 is disposed without spacing between the cells to reduce the block size. Then, the wirings of the block 6 at the center of the chip are more in the second layer wirings 10, 11 in Y direction A1 between the blocks at the center of the chip to be complicated. Consequently, the wirings are executed by avoiding the use of the second layer in the block A1. In other words, after the cells are spaced therebetween by considering the wirings exceeding the cell row to form the Y-direction wirings in the block in the silicide layer of a gate electrode in the disposition of the cell 7, the wirings in the block in Y direction is formed of the silicide layer. Then, the second layer in the block A1 is used for the wirings in the Y-direction between the blocks. |
