发明名称 ERROR CORRECTING SYSTEM AND ERROR CORRECTION DECODER
摘要 <p>PURPOSE:To offer the error correction system having a correction capability as if no error expansion by a descrambler were in existence by using a reception signal series after descrambling and a generation polynomial of the descrambler. CONSTITUTION:A generation polynomial g(x) being mutually prime to a generation polynomial f(x) of the scrambler is used, an error correction code is added to a transmission data to attain block coding. The coded signal is scrambled by using the generation polynomial being mutually prime with the generation polynomial g(x) of the check bit at the scrambler and the result is transmitted. A reception signal r(x) is subject to descrambling at the reception side. A syndrome pattern s(x) of each block is calculated by a reception signal u(x) subject to descrambling and a pattern s(x) is converted into an error pattern e(x) on a transmission line. On the other hand, a reception signal retarding the reception signal u(x) is subject to rescrambling to generate a signal on the transmission line. This signal is subject to error correction by using an error pattern on the transmission line and the transmission data is obtained by applying descrambling again.</p>
申请公布号 JPS61108228(A) 申请公布日期 1986.05.26
申请号 JP19840229506 申请日期 1984.10.31
申请人 NEC CORP 发明人 FURUYA YUKITSUNA;NAKAMURA KATSUHIRO
分类号 H03M13/00;H03M13/27;H04L1/00;H04L7/00;H04L25/49 主分类号 H03M13/00
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