发明名称 PARITY CHECK CIRCUIT
摘要 PURPOSE:To attain a parity check without applying a double constitution by adding a parity bit to the output of a data register to store it to a parity bit flip-flop and also to perform a parity check. CONSTITUTION:A parity check circuit is provided with the 1st and 2nd data registers 1 and 6, a parity generating part 2, a parity bit flip-flop 3, a parity check part 7, the 1st and 2nd timing flip-flops 4 and 5 and a parity error register 8. The data set to the register 1 is supplied to the part 2 with addition of a parity bit and then stored to the flip-flop 3. At the same time, the parity check is carried out through a parity check part 7.
申请公布号 JPS6194151(A) 申请公布日期 1986.05.13
申请号 JP19840214011 申请日期 1984.10.12
申请人 NEC CORP 发明人 KAWADA KAZUHIRO
分类号 G06F11/10 主分类号 G06F11/10
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