| 摘要 |
PURPOSE:To make a useless dummy processing flow unnecessary by providing an identifier for showing a fact that a branch format of the next instruction is a condition branch, in an instruction previous to an instruction for executing the condition branch, and delaying an address determination of the next instruction until a condition definite decision timing. CONSTITUTION:A micro-instruction read out of a storage device 11 is written on a data register 12, and an address generating circuit 15 generates an address of the next micro-instruction from a data register 12. In case when there is no condition branch, an identifier F is off, therefore, the address generating circuit 15 generates an address of the next micro-instruction and writes it in an instruction register 16. When a processing flow PFi-1 previous by one to a condition setting processing flow PFi is read out to the register 12, on of the identifier F is detected, a control signal is sent to a pipeline controller 13, the execution of the processing flow PFi-1 is set to a banding state in the end, the address generating circuit 15 turns on the identifier F, and an address of the micro-instruction to the condition branch processing flow PFi is generated. |
