| 摘要 |
PURPOSE:To reduce substrate resistance mainly by making impurity concentration in a lower section higher than that in the surface in impurity concentration in a well and maximizing impurity concentration where deeper than a junction depth with the well. CONSTITUTION:A B implanting layer 14 is formed partially in the depth 1.5mum of an N type Si substrate 11 and a P implanting layer 15 in higher concentration extending over the whole surface of the substrate in fixed width in depth 3.3mum, and a P well 21 and an N<-> layer 29, which have both 10<17>/cm<3> or more, are shaped through heat treatment. A P<+> source 17 and a drain 18 are shaped to the substrate 11 and N<+> source 22 and drain 23 are formed into the P well through a known CMOS technique, thus shaping a CMOSFET. An internal wiring 27 is formed through an insulating film 26, and coated with a protective film 28. According to the constitution, the steep distribution of an impurity can be formed to a large-diameter wafer, substrate resistance is lowered by the N<+> layer 29, a latch-up and a soft-error can be prevented, and the layer 29 is shaped through ion implantation, thus reducing the cost of the wafer, lowering a temperature on treatment and minimizing defect density, then obtaining high performance. |
