发明名称 FET INTEGRATED CIRCUIT
摘要 PURPOSE:To integrate an FET integrated circuit while preventing a source electrode and a drain electrode from migrating by forming the shapes of the source and drain electrodes substantially in a triangular shape that the electrode width of the top is reduced from the root, and bringing source and drain regions Approximately in coincidence with the electrode profile of the triangular shape. CONSTITUTION:A plurality of source electodes 10' extended from a source bus 11 and a plurality of drain electrodes 20' extended from a drain bus 21 are formed inthe isosceles triangular shape that the electrode width of the top is reduced from the root (electrode width l), and the shapes of source regions 1',... and drain and drain regions 2',... are brought substantially in coincidence with the electrodes 10',..., 20',... and contacted at C' in a triangular shape. The, a gate electrode 30' formed on channel regions 3', 3' formed in the relationship between the regions 1',... and the regions 2',... is formed integrally in a folded shape. Thus, the current density at the portion directed from the intermediate to the top of the electrode 10' becomes substantially constant without fear of a migration, and the electrode 20' is similar.
申请公布号 JPS6175565(A) 申请公布日期 1986.04.17
申请号 JP19840197506 申请日期 1984.09.20
申请人 SANYO ELECTRIC CO LTD 发明人 ISHIDA MICHIAKI
分类号 H01L29/78;H01L29/417 主分类号 H01L29/78
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