发明名称 Transfer circuit for defect inspection of an integrated circuit
摘要 A logic circuit is formed on a gate array chip together with a custom-circuit. Bonding pads mounted on the gate array chip are used as the terminals which send forth or receive data and control signals. The logic circuit is provided with a shift register for holding data to test the flip-flops of the custom-circuit and output data from the flip-flops. The shift register comprises the stages each of which holds 1-bit data selected by a read control signal. The output terminals of the stages are respectively connected to the input terminals of the flip-flops of the custom-circuit through the AND gates which are rendered conducting in response to a set control signal. The output terminals of the flip-flops are connected to the input terminals of the respective stages of the shift register.
申请公布号 US4581740(A) 申请公布日期 1986.04.08
申请号 US19830564194 申请日期 1983.12.22
申请人 TOKYO SHIBAURA DENKI KABUSHIKI KAISHA 发明人 KINOSHITA, TSUNEO
分类号 G01R31/28;G01R31/317;G01R31/3185;G06F7/00;(IPC1-7):G01R31/28 主分类号 G01R31/28
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