| 摘要 |
An interchangeable bus section addressing arrangement for electronic units 1, 2, 3, or the like which are connectable in an arbitrary sequence, wherein each unit includes a plurality of input address connectors 10, an identical plurality of output connectors 11, the input and output connectors being subdivided into corresponding groups a, b, c, d with the connectors in each input group being electrically coupled to the connectors in the corresponding output group, the number of connectors in each input group being different and likewise the number of connectors in each corresponding output group, the arrangement of the couplings between the input and output connectors of corresponding groups being such that for each group the order of the output (input) connectors is advanced by one with respect to the order of the input (output) connectors, each unit further including connection logic 12 having the same number of connections as the number of groups, said logic connections being connected one to a particular coupling in each group in identical fashion for all the units so that the units are provided with identical sections of an address bus whereby when the units are connected in sequence simultaneous selection 14 of one connection only in each group at one point in the sequence effects unique addressing of one of the units so connected. |
