| 摘要 |
PURPOSE:To detect an error without fail when a plural (irrespective of odd or even number) logic ''1'' state arises simultaneously by utilizing two priority encoders whose priority levels are reversely connected. CONSTITUTION:Outputs of eight FFs 1-8 for showing the logic ''1'' state are connected to inputs of priority encoders 20 and 21. At this time, since priority levels of the encoders 20 and 21 are reversely connected, outputs of the encoders 20 and 21 are encoded to a reverse pattern in terms of the normal state. Consequently, outputs of exclusive OR circuits 30-32 are of all logic ''1'', and an output signal 41 of an AND circuit 40 also comes to the logic ''1'' to show the normal state. When plural FFs 1-8 come to the logic ''1'' simultaneously, the outputs of the encoders 20 and 21 will not come to a reverse pattern, and any one of outputs of the circuits 30-32 comes to a logic ''0''. At the same time, the signal 41 also comes to the logic ''0'', and thus an error is reported to an error processing circuit. |
