| 摘要 |
<p>In a demodulation circuit, a timing synchronizing circuit (26) generates a timing signal representing a sampling timing of an A/D converter (19, 20) and has a timing signal generator (24, 25), a polarity identification circuit and a logic circuit (22). The timing signal generator (24, 25) is phase-controlled by a phase control signal and generates a timing signal. The polarity identification circuit (22) identifies a polarity of a differential coefficient of the baseband signal at a sampling point of the A/D converter (19,20) and generates a polarity identification signal. Upon logic processing, the logic circuit (23) supplies to the timing signal generator (24, 25) the phase control signal representing a deviation of an actual sampling point of the baseband signal from an optimal sampling point. A carrier asynchronism detection circuit (41) detects an asynchronism state of a carrier regenerating circuit (21) and supplies to the timing synchronizing circuit (26) a signal which changes its loop parameter.</p> |
