发明名称 SUPERCONDUCTION DELAY LINE MEMORY DEVICE
摘要 PURPOSE:To enlarge delay time per unit length at a superconduction delay line part and to make small delay time at wiring of a peripheral circuit part by prescribing film thickness of an insulator at a prescribed area on an earth plate. CONSTITUTION:Thickness of an insulation layer 3 of an area of a transmission line 4 at a superconduction delay part on an earth plate 2 is thicker than that of insulation layers 5, 9 and 11 of a peripheral circuit of a signal line 10, control line 7, etc., which are connected through a Josephson junction 8 to the line 4. For this reason, the delay time per unit length, which changes in accordance with an effective magnetic permeability in reverse proportion to thickness of an insulation layer becomes longer at the line 4 and shorter at the wiring of the peripheral part. As this result, signal propagation delay time per unit length of a transmission line for a delay line is made large, the peripheral circuit, which reads and writes information, operates speedily, information can be read and written at a high frequency and a superconduction delay line memory device with large memory capacity can be obtained.
申请公布号 JPS6139997(A) 申请公布日期 1986.02.26
申请号 JP19840160496 申请日期 1984.07.31
申请人 NEC CORP 发明人 NAGAI HAJIME
分类号 G11C21/00;G11C11/44;H01L39/22 主分类号 G11C21/00
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