| 摘要 |
PURPOSE:To prevent the generation of a latch-up by surrounding four sides of a P channel transistor by an N<+> layer and those of an N channel transistor by a P<+> layer and connecting the N<+> layer to a power supply line and the P<+> layer to a grounding line at a large number of positions in an output buffer section for a CMOS-IC. CONSTITUTION:In an output buffer section for a CMOS-IC, four sides of an N channel transistor 15 are surrounded by a P<+> layer 16, and the P<+> layer is connected to grounding line 27 at a large number of positions. Four sides are sur- rounded by an N<+> layer connected to a power supply line 32 at a large number of positions in a P channel transistor 23. Consequently, impedance 28 between the grounding line 27 and a P<+> layer 30 is reduced, thus rapidly sucking up substrate currents 26, 31 to the grounding line 27 from the P<+> layer 30, then preventing the generation of a latch-up. Currents intending to flow into a parasitic transistor 29 through a parasitic transistor 35 are also erased by currents 50 flowing through the N<+> layer 24 from the power supply line 32, thus further obviating the generation of the latch-up. |
