| 摘要 |
PURPOSE:To enable the reduction in memory cell area by a method wherein a groove-type capacitor is formed over the periphery of a memory cell, and a transfer gate is constructed inside thereof by means of a vertical MOSFET. CONSTITUTION:A laminated film consisting of an N type substrate 5, an Si oxide film 6, an Si nitride film 7, and a pad oxide film 8 is formed in the cell region of a P type Si substrate, and the groove 9 is formed. Next, a boron ion implanted layer 10 is formed at the bottom of the groove 9. Thereafter, the film 6 is removed and a capacitor oxide film 13 is formed on the side surface of the groove 9. In this state, poly Si 14 of low resistivity is deposited only in the groove 9, and a selective oxide film 111 is formed on its surface. Then, an Si oxide film 61 is deposited over the whole surface, and a groove 91 is formed at the center of the island A. An N type semiconductor layer 51 is formed at the bottom of the groove 91, and a gate oxide film 16, a poly Si 142, and an Si oxide film 17 are formed on the side surface of the groove 91; besides, poly Si 143 of low resistance is deposited in the groove 91. The transfer gate part composed of a vertical MOSFET is formed by patterning. |
