| 摘要 |
A shift register bit with first and second masters and a slave receives clocked data on the first master from two inputs. After data has been received by the first master, data is coupled from the first master to the second master. In the event that both clocked inputs are operative, the second master is coupled to the slave. One of the inputs is given priority. The other input is disabled. At a predetermined time the second master is decoupled from the slave and the first master is coupled back to the slave.
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