| 摘要 |
PROBLEM TO BE SOLVED: To arbitrarily set the width of phase difference by changing delay time by composing a lock detector of a delay circuit and a data flip-flop. SOLUTION: A reference clock signal REF100 is inputted to a delay circuit 103, and a clock signal CLK105 of phase delay is generated from the delay circuit 103. Besides, a generation clock signal 101 is inputted to a delay circuit 102, and a clock signal 104 of phase delay is outputted from the delay circuit 102. A data flip-flop 106 respectively adds the reference clock signal 100 and the phase delayed signal 104 of the generation clock signal, and the phase difference between the reference clock signal 100 and the generation clock signal 101 is compared with the delay time of the delay circuit 102. When the phase difference is less than the delay time of the delay circuit 102, a high level is outputted and when the phase difference is more than the delay time, a low level is outputted. Thus, by changing the delay time, the width of phase difference can be arbitrarily set. |
