发明名称 In-line solid state time delay device
摘要 A two-terminal in-line time delay device incorporating upon the initiation of in-put power into the device a pulsing component which, after a selected time delay, provides a gating pulse for a line-to-load series connected SCR. As the SCR is switched on, a connected transistor is turned on to provide a continuous gating current for the SCR which allows load-to-line current flow.
申请公布号 US4562366(A) 申请公布日期 1985.12.31
申请号 US19810336284 申请日期 1981.12.31
申请人 ZADEREJ, ANDREW;ZADEREJ, ANDREW J. 发明人 ZADEREJ, ANDREW;ZADEREJ, ANDREW J.
分类号 H03K17/292;(IPC1-7):H03K5/159;H03K17/60 主分类号 H03K17/292
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