| 摘要 |
An integrated circuit memory is provided wherein an array of memory elements is addressed by a decoder circuit responding to an address signal. The decoder circuit includes a plurality of sections, each one thereof being used to address a different section of the array. A decoder section selector is provided which, in response to the addressing signal, determines the section of the array being addressed and electrically couples the one of the plurality of decoder circuit sections which is coupled to such addressed array section to a power source while electrically decoupling the remaining section of the decoder circuit from such power source. With such arrangement, only a portion of the decoder circuit is electrically coupled to the power source when addressing the array thereby reducing the power consumption of the integrated circuit memory.
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