| 摘要 |
PURPOSE:To simplify the constitution and high-speed processing of a run length code by providing an ROM sequencer inputting in parallel the run length code. CONSTITUTION:A run length code 104 from a control section 101 is fed to the ROM sequencer 102 while being in parallel, after the code is decoded altogether, decoded data 105 is outputted, returned to the control section 101, and a required run length code is outputted via prescribed processing. A 1-bit shift register 103 is connected in parallel with the sequencer 102, which applies decoding every time 1 bit is inputted, the bit is inputted to the register 103 via an I/O signal line 106, the next bit is decoded while the bit is shifted, and after the decoding is finished, the decoded data 105 is returned altogether to the control section 101. |
