| 摘要 |
PURPOSE:To output a count value of a clock signal while dividing it N-time by x-bit each by inputting an AND value of carry outputs of the 1st-(i-1)th counters to the 2nd enable terminal of the 1-th counter. CONSTITUTION:A value of an output signal 7 of a counter A is ''0'' when a 1/3 frequency division signal 2 is at a low level. When the 1/3 frequency division signal 2 goes to a high level, ''0'' is loaded, and the counter a counts up and the value of the output signal 7 of the counter A changes from ''0'' to ''1''. Since the 1/3 frequency division signal 2 goes to a low level during two clocks afterward, the value of the output signal 7 of the counter A remains ''0'' and unchanged. When the 1/3 frequency division signal 2 goes to a high level, a value ''1'' of the preceding output signal 7 is fed back and becomes an input to the counter A, loaded and then counted up, then the value of the output signal of the counter A changes from ''1'' to ''2''. Then the counter is counted up at three clocks each.
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