CACHE MEMORY CONTROL CIRCUIT

摘要

PURPOSE:To attain data processing with no conflict by holding the data on access to a specific area at a cache memory in case a processor gives access to a memory means having varying memory contents. CONSTITUTION:For an instruction control circuit 10, a read signal 114 is turned on by an inverter 28 and an AND gate 29 to indicate reading to an external memory when a signal 112 turns on since a signal 119 is kept off in case an associative memory 20 stores no read data. At the same time, a comparator 19 compares an address signal 116 with the values of registers 16 and 17. A signal 115 is turned off in case an address is set between the lower and upper limit values held in a register. The external memory outputs the read data to a signal 121 when the reading action is over and turns on an end signal ACK113. Thus a signal 110 is turned on via an OR gate 23. Then the circuit 10 writes the data read out to a register 14 to complete its operation.