发明名称 METHOD FOR FORMING CONTACT OF INTEGRATED CIRCUIT
摘要 PURPOSE:To improve stability and reliability of contact by lowering a resistance of contact of integrated circuit by introducing N type impurity to a solid phase epitaxial layer precipitated by a low temperature annealing. CONSTITUTION:An aperture of 2-3mum square is opened on an insulation film 12 of PSG provided on a silicon substrate 11. Next, a first conductive metal layer 13 is formed and low temperature annealing is carried out at the temperature lower than the melting point of aluminum, for example, in the range of 400-550 deg.C under the N2 or Ar gas ambient. A Si layer 14 (solid phase epitaxial layer) is formed in the thickness of 200-2,000Angstrom by such low temperature annealing. Thereafter, a first conductive metal layer 13 is eliminated and the precipitated Si layer 14 is exposed by immersing the device into ferro-acidic aqueous solution at 50 deg.C. The N type impurity is diffused into the precipitated Si layer 14 by any of the well known gas phase diffusion, solid phase diffusion or ion implantation, so that the precipitated Si layer having a high resistance can be converted to a conductor having a low resistance. In case a second conductive metal layer 15 is formed with 100% aluminum, or aluminum including Si or other conductive metal, a stable contact can be obtained because a conductive precipitated Si layer exists between the Si substrate 11 and the second conductive metal layer 15.
申请公布号 JPS60254725(A) 申请公布日期 1985.12.16
申请号 JP19840111443 申请日期 1984.05.31
申请人 FUJITSU KK 发明人 SATOU NORIAKI;SUGITA MASAO
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
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