发明名称 TIMER SETTING SYSTEM
摘要 <p>PURPOSE:To make respective timer values coincide with each other at each time precisely by forming exclusive clocking timers in respective processors and also forming a timer starting means consisting of an exclusive signal line. CONSTITUTION:In this system, (N+1) processors (1-0)-(1-N) having individual clocking timers in their inside, a processor (X)2 previously clarified that there is no possibility to execute a timer setting instruction or a timer reading instruction and having no clocking timer and a main memory 3 are mutually connected through a system common bus 1000 to transmit/receive commands, data and other information between the processors through the bus 1000. In addition, the exclusive timer starting line 100 is connected among respective processors (1-0)- (1-N) having clocking timers in their inside. The respective clocking timers included in the system are simultaneously set through the exclusive line 100 when an optional processor in the processors (1-0)-(1-N) executes the timer setting instruction.</p>
申请公布号 JPS60254364(A) 申请公布日期 1985.12.16
申请号 JP19840111336 申请日期 1984.05.31
申请人 NIPPON DENKI KK 发明人 YOSHITAKE MASAAKI
分类号 G06F15/16;G06F1/14;G06F9/52;G06F15/17;G06F15/177 主分类号 G06F15/16
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