发明名称 PROCESSOR DOWN INFORMING SYSTEM
摘要 PURPOSE:To reduce the number of signal lines for supervising by informing processor down utilizing unused time of a common bus. CONSTITUTION:When a cause 213 of processor down occurred, a processor down signal forming circuit 210 outputs pulse of 1 clock width that becomes a processor down signal only when a bus busy signal 43 that indicates a common bus 4 is in use is off. The pulse signal of a processor down output 214 makes a processor down signal line 41 effective through an inverter 211, and pulse of a down processor number 215 makes an address signal line 42 selected by a change-over switch 212 effective. Other processor down detecting circuit 22 detects that the signal line 41 is made effective, and outputs a request 101 for interruption by processor down to a processor not shown in the figure, and at the same time, sets the downed processor number sent on the address signal line 42 of a down processor number display register 23 to a flip-flop 231.
申请公布号 JPS60252962(A) 申请公布日期 1985.12.13
申请号 JP19840109880 申请日期 1984.05.30
申请人 FUJI DENKI SEIZO KK;FUJI FUAKOMU SEIGIYO KK 发明人 SUZUMURA YASUNARI;KOYAMA MINORU
分类号 G06F11/30;G06F15/16;G06F15/177 主分类号 G06F11/30
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