发明名称 DIGITAL PHASE LOCKED LOOP
摘要 PURPOSE:To eliminate a stationary phase error by a simple constitution, by providing an integral element of an output of a phase comparator, switching as a time division the respective outputs of this integral element and the phase comparator, and providing them to a loop filter. CONSTITUTION:In case a frequency of a read-out signal RS is shifted from a center frequency fC due to an influence of a jitter, etc., a phase difference data corresponding to this frequency difference is stored in a counter (integrating counter) 11, a signal S11 of a corresponding pulse width and a signal S12 corresponding to its code are outputted, applied as a time division to a counter 2, and a frequency of a frequency signal FS is controlled so as to be equal to the read- out signal RS. Output signal S1, S2 of a phase comparator 1 are also applied as a time division to the counter 2 through a multiplexer 13, and by this system, a phase difference of the frequency signal FS and the read-out signal RS is controlled so as to become ''0''.
申请公布号 JPS60245312(A) 申请公布日期 1985.12.05
申请号 JP19840099690 申请日期 1984.05.19
申请人 RICOH KK 发明人 SHIGEMORI TOSHIHIRO
分类号 G11B20/14;H03K23/66 主分类号 G11B20/14
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