| 摘要 |
PURPOSE:To obtain a logic circuit of a stable and high speed operation by delaying successively an input clock signal of an edge trigger type flip-flop of each stage, in the direction opposite to a flow of a data signal. CONSTITUTION:When an input signal D1 is inputted to an edge trigger type flip- flop 11 by synchronizing with a clock CP5 having a delay time of 5t1, the FF11 is set by synchronizing with a clock CP4 having a delay time of 4t1, and an output D2 is inputted to an FF12 of the next stage. Thereafter, the FF is set successively, and an FF14 of the last stage is set by a CP1 having no delay and provides an output D5. In this way, the FF of each stage is operated by the clock when the output of the FF of the previous stage is in a high level, therefore, the stable operation can be executed. |
