发明名称 DATA SCANNING PROCESSING SYSTEM
摘要 PURPOSE:To improve the ability of microprogram control in scanning processing without adding any hardware by nesting comparing data in a RAM so that the final data of a record is in the tail address of the RAM. CONSTITUTION:The head address of the 1st record from a microprocessor muP1 is loaded in an address register 4 and the address obtained by subtracting one record length from the tail address of the RAM3 is loaded in an address register 2. Further, a chip select signal CS is sent out to RAMs 3 and 5, which are accessed on the basis of the contents of the registers 2 and 4 to read respective data. Those data are inputted to the muP1, which compares and collates those data to sent a 1-count-up indication UP to the registers 2 and 4 when the input data coincide with each other. Thus, when the register 2 counts up to the address of the final data of one record, an overflow signal 7 is inputted to the muP1, which knows the completion of the comparison and collation of the 1st record and checks whether the condition are satisfied or not.
申请公布号 JPS60245047(A) 申请公布日期 1985.12.04
申请号 JP19840100495 申请日期 1984.05.21
申请人 HITACHI SEISAKUSHO KK 发明人 NAKAMURA MASAYUKI;HORI KAZUYA;KINOSHITA NOBORU;TSUCHIYA CHIHIRO;HIRATA SUNAO
分类号 G06F7/04;G06F9/22;G06F17/30 主分类号 G06F7/04
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