| 摘要 |
<p>PURPOSE:To prevent a no-break memory from incorrect writing due to the runaway of a program by inhibiting writing ordinally, forming a write inhibition releasing signal only at a writing time and impressing AND between the release signal and the writing signal to a non-volatile RAM. CONSTITUTION:Ordinarlly, an H level reading signal is impressed from a gate 6 to the R/W terminal of the non-volatile RAM(NVRAM)4, data reading is available and writing is inhibited. When a data writing request is generated, an L level signal S'w for releasing write inhibition is outputted from the PA1 terminal of an interface 15 to the gate 16. Since a write request signal W'R' is outputted from a CPU1 to the gate 16, the output of the gate 16 is turned to the L level and a write signal W'R' is impressed to the NVRAM4. The NVRAM4 stores data obtained from a data bus 5 in an address area selected by a chip selector signal C'S' outputted from an address decoder 7.</p> |
