| 摘要 |
PURPOSE:To shorten the processing time which is spent to stop the instruction execution of a processor in a desired address position, by switching the operation mode to the operation mode, where instructions are prefetched and executed, and the operation mode where instructions are not prefetched and executes. CONSTITUTION:In case that the instruction execution of the processor is stopped in a position (1), an address A2 is set to a stop address setting register 15, and an address A0 preceding it is set to a near address setting register 16. When instructions preceding an instruction 00 in the address A0 are executed, a signal 23 is made ineffective, and the processor 11 executes instructions in the operation mode where instructions are prefetched. When the address value A0 is outputted onto an address bus 14, signals 22 and 23 are made effective, and the opertion mode of the processor 11 is switched to the operation mode where instructions are not prefetched. When an instruction 02 in the address A2 is executed, a signal 21 is made effective to generate a stop interrupt signal, and the stop interruption processing is performed after execution of the instruction 02. |
