| 摘要 |
A level sensitive scan design (LSSD) Latch Cell that is adaptable to very large scale integrated (VLSI) Semiconductor circuit fabrication is disclosed. The Latch Cell includes a static functional latch and a dynamic test latch, both of which are controlled by a data selector that selects input data from either a functional data source or test data from another test latch in a scan data path.
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