| 摘要 |
<p>PURPOSE:To prevent a system from being locked due to malfunction of a device for transmitting a bus request by providing a preset counter in a CPU, and monitoring a state of a signal by said counter. CONSTITUTION:A bus request signal, a bus transaction start timing signal and a clock signal are supplied to a controlling circuit 11, and a count signal and a preset signal outputted from the controlling circuit 11 are supplied to a preset counter 12. Also, the counter signal and the preset signal outputted from the controlling circuit 11 are supplied to a preset counter 15. A signal for indicating a fact that the contents of the counters 12, 15 have become ''0'' is applied to a set input terminal S of a flip-flop FF1 through an OR circuit 18, and from an output terminal of this flip-flop FF1, a bus occupation inhibiting signal is outputted. This signal is made valid or invalid by an output of the flip-flop FF2.</p> |
