| 摘要 |
PURPOSE:To attain high speed test by dividing an area of an AND input line into plural numbers and constituting an area so that a logical value of the product term line at test is made independent of the input data of an input line of other area thereby decreasing the number of combinations of possible input data. CONSTITUTION:Eight AND input lines 1, 1... of a programmable logic array (PLA) are divided into two areas a, b comprising four inputlines 1a-1b, and product term lines 2a, 2b between the divided areas (a) and (b) are made respectively independent. Product term lines 2a, 2a...2b, 2b... are connected respectively to inputs of AND gates c, c... and also to inputs of area selection data selectors d,d.... The selector (d) selects the data of the product term 2a or 2b of the area (a) or (b) by using an area selection signal (e). The number of input patterns is 2n in a conventional PLA when all combinations of the AND input line numbers (n) are tested. In dividing the input lines into two as shown in this example, the number is 2<n/2>X2, the input pattern number is less and the test time is decreased. |
