| 摘要 |
PURPOSE:To prevent oscillation stop through a simple circuit by using a set and reset type FF and a rectifying element and a logic inverting element which set said FF when a capacitor voltage rises above a reference voltage. CONSTITUTION:When the voltage of the capacitor 3' becomes higher than the reference voltage, the output of a comparator 7 goes up to H and the RS type FF10 is set. The output of a logical element 7, on the other hand, is delayed by a specific time through gates 8 and 9 and the FF10 is reset with the leading edge of a pulse. When oscillation stops, the capacitor 3 is discharged with a signal current is and its voltage becomes much higher than the reference voltage. In this state, a diode 11 conducts and the gate 9 receives an input H and generates an output L. Therefore, the FF10 outputs H and an SW turns on, so the capacitor 3 is charged and the voltage drops. When this voltage drops below the reference voltage, the oscillation restarts. |
