| 摘要 |
PURPOSE:To simplify the circuit configuration of a 2/3-frequency division circuit digitized for the entire circuit, by providing an 1/3-frequency difision circuit, shift register, and a logic circuit. CONSTITUTION:A pulse (a) having a duty of 1:1 from the input terminal 1 of a 2/3-frequency division circuit is inputted in an 1/3-frequency division circuit 2 and the circuit 2 divides the frequency of the pulse (a) into 1/3 and outputs a pulse (b) whose ratio of high level period to low level period is 2:1. The output pulse (b) is inputted in a shift register SR1 and delayed by the one cycle of the input pulse (a) by means of the input pulse (a) from a clock terminal CK. Then the input pulse (a) is inverted by an inverter 3 and the AND of the inverted one and output pulse of the register SR1 is taken at the 1st AND circuit 4. The output pulse (e) of the AND circuit 4 is inputted in one side terminal of an OR circuit 6. Moreover, the AND of the output pulse (b) and the input pulse (a) is taken at the 2nd AND circuit 5 and the output pulse (d) of the circuit 5 is inputted in the otherside terminal of the OR circuit 6 and a pulse (f) whose frequency is divided into 2/3 is outputted from an output terminal 7. |
