| 摘要 |
PURPOSE:To attain reduction of circuit scale and also excellent general-purpose application by multiplying elements of a definite body of vector expression without using any memory. CONSTITUTION:One arithmetic circuit is constituted by a converting circuit 17 generating each element of a (8X8) matrix T1 by a eight-bit input and with a multiplication gate 19 multiplying an eight-bit input A and an element from the converting circuit 17 via a D flip-flop 18, and the other arithmetic circuit is constituted by a converting circuit 25 generating each element of a matrix T2 and a multiplication gate 28 multiplying an output of a multiplexer 27 via a D flip- flop 26 and an element from the converting circuit 25. Outputs of the multiplication gates 19, 28 are fed to an adder of (mod.2) comprising an EXOR gate. An output of the adder 29 is extracted as an output C via a D flip-flop 30. The arithmetic circuits generate a syndrome of various error correcting codes or generate a parity of various error correction codes. That is, the elements of the definite body of vector expression are multipled without using any memory.
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