发明名称 PERFECCIONAMIENTOS INTRODUCIDOS EN UN CIRCUITO DE TRATAMIENTO DE SENAL
摘要 <p>A signal processing circuit is provided which comprises: a plurality of cascaded delaying means 10, 12, 14, 16, 18 successively delaying input signals; a means 100 for detecting magnitude changes of the input signals; and selective coupling means 20, 22 responsive to the detecting means, for selectively coupling the inputs of certain of the delaying means to the inputs of selected others of the delaying means to enhance the transition times of input signals, thereby providing sharper edges at colour boundaries in a video signal. <IMAGE></p>
申请公布号 ES534491(D0) 申请公布日期 1985.11.01
申请号 ES19910005344 申请日期 1984.07.20
申请人 RCA CORPORATION 发明人
分类号 H04N5/21;H03K5/12;H04N5/208;H04N9/64;H04N9/68;H04N9/77;(IPC1-7):H04N9/68 主分类号 H04N5/21
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