| 摘要 |
PURPOSE:To share a control signal with plural instructions and to simplify the constitution of a gate circuit by attaining the transfer of data despite the difference between the data transmission and reception timings. CONSTITUTION:A data bus 1 is precharged with the timing of T1A for a microcomputer which transfers data between internal circuits by a data bus. A system clock T1B is delivered to a control signal OBD from an AND gate 26 with the timing of the T1B. While an output driver circuit 20 sends data B to the bus 1. Input gate circuits 24 and 22 fetch the data B on the bus 1 with timings of T2B and T3B and store it to circuit blocks C18 and A16. The data sent to the bus 1 is held although the data transmission timing is fixed. Thus it is possible to fetch data from the bus 1 with different timings. |
