| 摘要 |
PURPOSE:To reduce the probability falling into false synchronization and to shorten a synchronization reset time by forming two circuits for comparing and detecting the polarity of a frame marker bit and data to compare continuously and detect two bits of data. CONSTITUTION:Coincidence/inconsistency of the polarity of a frame marker bit with that of a data bit is detected through a received frame synchronization counter 1 and a comparator/detector 3. On the other hand, the 2nd comparator/ detector 7 having the similar function to that of the 1st one 3 is also connected. The 2nd comparator/detector 7 detects the coindidence/inconsistency of the polarity if received data obtained after one bit from the received data compared by the 1st comparator/detector 3 with that of said frame marker bit and a latch circuit 8 latches the detected result. When the 1st and 2nd comparators/detectors 3, 7 generate inconsistent outputs, a shift pulse generating circuit 9 outputs a shift instruction of two bits to the reveiving counter 1 to shorten the time up to synchronization. |
