| 摘要 |
The present invention features an ADPCM decoder of the instantaneous companding type which comprises two memory circuits (each preferably PROM). The first memory contains a plurality of differential values and the second a plurality of step size control codes. The memories receives ADPCM input codes which function as address signals. The memories are connected through an adder and a shift register feedback connected with the adder. The first memory receives two inputs, one of which is an ADPCM input code and the other is an input consisting of the sum of the current output of the second memory plus the previous value outputted thereby. The first memory produces a differential value on the basis of the two inputs applied.
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