MEMORY CONTROLLER AND MEMORY INSPECTOR

摘要

Data processing system, comprising a device provided for bypassing the main parallel data bus (11) between the processor (12) and main storage unit (14) by a serial data bus (19) for testing purposes. Serial test data is applied through the serial data bus (19) to a storage controller (13) which interfaces between the processor (12) and storage unit (14). The controller (13) includes means for converting the data from the serial bus (19) into the parallel format of the data which is provided (12) from the processor along the main parallel bus (11).