| 摘要 |
PURPOSE:To increase the speed of operation of an integrated circuit by inhibiting floating capacitance and miniaturizing gate length by forming a channel region through ion implantation and shaping source and drain regions in the channel region in a self-alignment manner through ion implantation while using a gate section as a mask. CONSTITUTION:A field oxide film 42 and a film 43 are grown on a silicon substrate 41, and an Si3N4 film 45 is deposited on the whole surface of a polycrystalline silicon film 44. The film 45 is patterned, and an oxide film 46 is grown on the exposed polycrystalline silicon film 44. An Si3N4 pattern 45' is removed and boron ions are implanted, a tungsten film 48 is grown selectively on the exposed polycrystalline silicon film 44, and the oxide film 46 and the polycrystalline silicon film 44 section are removed through etching and a gate electrode 49 is shaped. Arsenic ions are implanted while employing the gate electrode 49 and the field oxide film 42 as masks, and N<+> source and drain regions 50, 51 are formed through activation. The speed of operation is increased by shortening gate length. |
