发明名称 DOUBLE LOOP TRANSMITTER
摘要 PURPOSE:To attain the relief of a synchronizing signal with simple control by allocating exclusively the synchronizing signal to time slots so that the synchronizing signal areas are not included in the same time slot number between two loops. CONSTITUTION:If the transmission is impossible with a digital transmission line L2, the OR information of switch memories SM1 and SM2 is outputted to a control signal CSM1. While a remote station extracts a frame header signal FH1 that obtained the OR between the synchronous and a synchronous section indicating signals of the line L2 out of the frame information on the line L2. Then a link memory has the same actuation as that of a normal mode. At the same time, the information stored to the memory SM2 can also be outputted to the signal CSM1 like the information of the memory SM1. Thus it is possible to relieve also the terminals connected to other digital transmission lines.
申请公布号 JPS60203040(A) 申请公布日期 1985.10.14
申请号 JP19840060185 申请日期 1984.03.27
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 OIKAWA YOSHINORI;TOKURA NOBUYUKI;KIMURA YUKIO
分类号 H04J3/24;H04J3/14;H04J3/16;H04L12/437 主分类号 H04J3/24
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