Modular data processing system.

摘要

A modular data processing system having a plurality of discrete functional hardware circuit modules, each circuit module being connected to a common system bus and at least part of the modules having control circuitry for intermodule communication in which they perform particular tasks using distributive processing technique, each of these modules having a central processing unit (CPU). The control circuitry comprises: interrupt register means (302) and response port means (300) in each of the modules; means (IOWC) for writing a given code into the response port of the target module; means (IORC) in the calling module for reading the code in the response port of the target module; and means (IOWC) in the calling module for loading the interrupt register in the target module with a multibit vector only if said calling module has read said code from the response port of the target module; and means (RDIR) for causing the target module to read the vector stored in said interrupt register whereby said target module is caused to perform a task associated with said multi-bit vector.