发明名称 MEMORY ADDRESS CONTROL SYSTEM
摘要 PURPOSE:To read out image information as normal erect data even if the information is stored as inverted data by forming a circuit for converting reading addresses. CONSTITUTION:When if a read-out original is discriminated as an inverted one, a control signal C1 is outputted from a CPU and an FF18 is set up. Address selectors 11, 12 outputs address data selectively from corresponding address converting circuits 16, 17 and send the address data to an image memory 3. The memory 3 is specified at its addresses successively from the final address and data in the memory 3 are read out in the reversed order against the writing order. If the original is discriminated as a normal erect one, the FF18 is reset as it is, the address selectors 11, 12 output address data from the CPU as they are and the memory 3 is specified at its addresses successively from the leading address.
申请公布号 JPS60196859(A) 申请公布日期 1985.10.05
申请号 JP19840053290 申请日期 1984.03.19
申请人 CASIO KEISANKI KK 发明人 NISHIO KIYOKAZU
分类号 G06F12/00;G06F12/02 主分类号 G06F12/00
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