| 摘要 |
PURPOSE:To facilitate easy conversion into an IC and to prevent a malfunction due to a clock delay by storing the 1st FF input signal during inversion of the 1st phase of a clock to supply the input signal to the 2nd FF and then obtaining the stored signal from the 2nd FF during inversion of the 1st phase of the clock which is supplied to the 2nd FF with inversion of the phase. CONSTITUTION:D-type FF circuits FF1 and FF2 constitute a shift register ST and have the same constitution, and master FF11 and FF11' are provided together with slave FF12 and FF12'. A digital signal D11 supplied to the FF11 is stored synchronously with a rise edge, for example, during the phase inversion of a clock signal CLK and then supplied to the FF12 as an output Q11. The FF12 shows the stored Q11 at the rise, for example, of the clock signal obtained by giving the phase inversion to the signal CLK. Therefore outputs Q11 and Q11' of FF11 and FF11' have level changes by the rise edge of the CLK. In such a case, however, the output Q12 and Q12' of FF12 and FF12' are delayed and have level changes by means of inverters 21 and 21'. Thus a malfunction is avoided even in case a clock has an irregular delay. |
