| 摘要 |
PURPOSE:To attain sure interlace without pulse noise and sag by using a digital circuit so as to extract plural vertical synchronizing signals, detecting a vertical synchronizing signal at the head and resetting a frequency divider. CONSTITUTION:A pulse generating circuit 9 generates a pulse having a pulse width being nearly 1/2 of the horizontal scanning period in synchronizing with an output signal of a horizontal oscillation circuit 3. The pulse is fed to a vertical synchronizing signal extraction circuit 10 together with a composite synchronizing signal from an input terminal 1 and plural pulses (vertical synchronizing signals) are outputted at each frame. The output is fed to a timing pulse generating circuit 11 detecting only the leading of the head pulse of the vertical synchronizing signal at each extracted frame and a set pulse rising the head vertical synchronizing signal is formed. A frequency division circuit 7 is reset by th reset circuit and a vertical pulse is obtained at an output terminal 8.
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