| 摘要 |
PURPOSE:To allow an MPU to read an input data correctly by allowing a counter control circuit to block a pulse input from an input device to a counter from the start of read of a byte of the counter to the end by the MPU. CONSTITUTION:A counter control circuit 6 is provided between a pulse input section and the counter. Through the constitution above, when a high-order byte read signal 2 is generated, the counter control circuit 6 checks the state of a pulse signal 1 from an input device, and when the pulse state possible for generation of a leading edge is at ''L'', a counter gate control signal 4 is turned off and after a low-order byte is read by a low-order byte read signal 3, the control signal 4 is turned on, the signal 1 is arisen and converted into a counter clock signal 5. Thus, the hardware counter of plural bytes possible for read by the MPU is realized.
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