发明名称 MULTILAYER INTERCONNECTION MEMBER
摘要 PURPOSE:To obtain an excellent electrical connection by a method wherein, when the upper wiring is to be connected to the underlying wiring, an interlayer insulating layer is covered on the underlaying wiring, the insulating layer is removed corresponding to the connected part, a connection hole burying layer is filled therein surrounded with an etching preventing member, and the upper wiring is brought to come in contact with the burying layer. CONSTITUTION:An insulating film 2 is coated on an Si substrate 1, the first layer of Al source wiring 3A and a fine Al wiring 3B are formed thereon, and an interlayer insulating layer 4 is coated on the whole surface including the above-mentioned layer and wirings. Then, the insulating layer 4 located on the wirings 3A and 3B is removed, and an Al burying layer 7 is filled in the part where the layer 4 was removed while said part is being surrounded by a Ti-W alloy or the etching preventing member 6 consisting of Cu. At this time, an etching preventing member 6 is provided on the bottom face and the side wall of the wiring 3B, but on the wiring 3A of large area, an aperture is provided on the etching preventing member 6 located on the bottom face. Subsequently, the second layer of wirings 8A and 8B are connected to the wirings 3A and 3B through the intermediary of the etching preventing member 6, and the semiconductor device is protected by covering a protective layer 9 on the whole surface.
申请公布号 JPS60187039(A) 申请公布日期 1985.09.24
申请号 JP19840042021 申请日期 1984.03.07
申请人 HITACHI SEISAKUSHO KK 发明人 MURATA JIYUN
分类号 H01L21/3213;(IPC1-7):H01L21/88 主分类号 H01L21/3213
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