发明名称 MULTIPLE ACCESS SYSTEM
摘要 PURPOSE:To reduce the block rate of line acquisition to enhance the line efficiency by securing the regularity of order of time slots even if time slots are assigned discretely on an outgoing-side highway in digital exchange. CONSTITUTION:For the purpose of transmitting first data A while preserving the regularity of order of time slots (TS), a TS having a minimum number (ITS5) between TSs having numbers (ITS5 and ITS10) larger than the first number ITS2 of incoming-side TS numbers is selected from TSs having numbers OTS0, OTS5, and OTS10 on an outgoing-side highway 30 hunted discretely, and this selected TS is defined as the origin of logical numbers. TSs are rearranged cyclically in order of OTS5, OTS10, and OTS0, and TSs having numbers OTS5, OTS10, and OTS0 on the outgoing-side highway 30 are allowed to correspond to TSs having numbers ITS2, ITS3, and ITS4 on an incoming-side highway 20 and are transmitted onto the outgoing-side highway 30.
申请公布号 JPS60183850(A) 申请公布日期 1985.09.19
申请号 JP19840038633 申请日期 1984.03.02
申请人 HITACHI SEISAKUSHO KK 发明人 TAKASHIMA KATSUHIKO;SAKURAI YASUO;ATSUMI TOSHIAKI
分类号 H04L12/52;H04Q11/04 主分类号 H04L12/52
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